Dr. pooja.kuppan

Senior Engineer · VLSI

Intel Corporation

Author

APID

11233

ORCID

0009-0009-5483-2279

Location

Folsom, California, United States

Expertise

VLSI Circuits

Areas of interest

power electronics, low power designs/applications, power-aware circuits, semiconductors, electronics, VLSI implementation, Digital circuits, design-for-reliability, and related physical design topics.

Member since

October 2025

Publications

1. Area Efficient Hardware Architecture of Spiking Neural Networks Based on Sign-Magnitude Stochastic Computing
2. Post-Route Glitch Power Minimization in SoCs: A Practical Flow for Real Silicon