sateesh kourav

JUNIOR RESEARCH FELLOWSHIP (JRF) · ece

Indian Institute of Information Technology, Design & Manufacturing, Jabalpur

Author

APID

2200

ORCID

0009-0003-2493-9717

Google Scholar

https://scholar.google.com/citations?hl=en&user=WVtw2fQAAAAJ

Location

JABALPUR, MADHYA PRADESH, India

Expertise

Electronics

Areas of interest

FPGA

Member since

April 2023

Biography

As a Junior Research Fellow in the Department of Electronics and Communication Engineering, I contributed to research projects focused on embedded systems and VLSI design. Master of Technology (M.Tech) in Embedded System & VLSI Design Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2022] Specialized in Embedded Systems and VLSI Design, with a focus on digital electronics, hardware-software integration, and advanced circuit design. Bachelor of Engineering (B.E.) Electronics and Communication Engineering] Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2019] Completed foundational studies in engineering, gaining a broad understanding of electronics, digital systems, and related technologies. Publications: I have published 14 research articles in prestigious national and international journals, demonstrating my expertise and contributions to the field of Embedded Systems and VLSI Design.

Hardware-Software Integration: Skilled in integrating hardware and software components to create efficient and reliable embedded systems.
Programming Languages: Proficient in Verilog and VHDL for hardware description and system design.
Design Tools: Experienced with a variety of design tools, including Diptrace, Origin, Layout Editor, Draw.io, Microsoft Visio, Symicade, and Cadence.

Publications

1. A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction
2. Area And Speed-Efficient Vedic RISC Processors for Embedded Systems
3. Area and Speed-Efficient Floating-Point Arithmetic Logical Unit Implementation on FPGA
4. Design and Analysis of Low Power, High Speed 64-Bit Alu Using Efficient Technique
5. Design and analysis of a high bandwidth patch antenna loaded with superstrate and double-L shaped parasitic components
6. Strategic design of asymmetric graphene and ReS2 field-effect transistors using nonlinear optimization and machine learning
7. ‘Analysis of high Performance 6-Stage 64-Bit MIPS RISC Pipelined Processor Using FPGA VHDL’